1. Field of the Invention
The present invention relates to a semiconductor sensor chip used in a wide range of applications such as automobile, aircraft, medical service, measurement, and calibration, and to a production method for manufacturing the sensor chip. It also relates to a semiconductor sensor comprising the semiconductor sensor chip, and to a package for assembling the semiconductor sensor.
2. Description of the Related Art
An example of a conventional acceleration sensor chip disclosed in Japanese Patent No. 2551625 is shown in FIG. 1A and FIG. 1B. FIG. 1A is a perspective diagram, and FIG. 1B is a sectional diagram taken along line IB--IB of FIG. 1A. In this semiconductor acceleration sensor chip, a silicon single crystal is etched to form a support frame 1, weight parts 2a and 2b, a beam part 3a for connecting the weight part 2a and the weight part 2b, and beam parts 3b and 3c for connecting the weight part 2a, the weight part 2b and the support frame with each other. Gauge resistors 4a, 4b, 4c, and 4d are provided on the beam parts 3a, 3b, and 3c, and a Wheatstone bridge is formed of these gauge resistors. When an acceleration is exerted in a direction shown by the arrow in FIG. 1B, resistances of the gauge resistors are changed. The acceleration sensor chip measures the acceleration utilizing changes of the resistances.
In general, in the semiconductor acceleration sensor chip of this kind, a silicon substrate is deeply etched from the backside to form thick-walled weight parts of about 300 .mu.m to 400 .mu.m and thin-walled beam parts of about 10 .mu.m to 50 .mu.m. As the silicon substrate, a 4 inch wafer is often used. The reason for this is as follows:
Because the substrate is required to be deeply etched to form a thin beam part, a small wafer thickness is advantageous in terms of productivity due to the limitation of processing time. A wafer size which can be handled in the process with a thickness of about 300 .mu.m to 400 .mu.m, corresponding to the thickness of the beam part, is bout 4 inches, and a larger wafer of 5 or 6 inches is substantially difficult to handle. Further, as shown in FIG. 1B a wafer before dicing is formed with a number of thin-walled, low resonance frequency beam parts and is low in rigidity. A shock applied during dicing tends to generate a resonance phenomenon of the sensor part or the wafer itself, and there is a danger of an excessive displacement or stress applied to the beam parts. Consequently, the wafer size is limited because of this handling.
In the case of the above-described semiconductor acceleration sensor chip, a greater part of the cost is determined by chip size and wafer size. When acceleration sensor chips are produced with the same technical level, if the wafer size is large, a large number of chips can be processed in a single batch process, and the unit price of the chip is naturally reduced. However, in the above-described prior art, usable wafer size is limited, and cost reduction can only be achieved by reduction of the chip size. However, the chip size reduction is limited as it may reduce production yield. Further, in the future, with the trend to larger diameter semiconductor wafers, a decrease in supply of 4-inch wafers is anticipated. If such an acceleration sensor chip is achieved with larger-diameter wafers of 5 inches, 6 inches or the like, a beam part of 10 .mu.m to 30 .mu.m in thickness must be formed from a silicon substrate of about 600 .mu.m to 700 .mu.m in thickness, which not only increases the etching time but also leads to a reduced production yield.
Another example of a prior art acceleration sensor chip is one which is disclosed in Japanese Laid-Open Patent Application No. 8-248058.
The second prior art example will be described with reference to FIGS. 2A and 2B. FIG. 2A is a perspective diagram of the acceleration sensor chip. FIG. 2B is a schematic diagram showing the structure of a comb electrode unit as part of the acceleration sensor chip.
This acceleration sensor chip has a three-layered structure comprising a first layer (support plate) 10, a second layer 11 as an insulation layer on the first layer, and a third layer 12 coated thereon. For example, it comprises a SOI (silicon-on-insulator) or epitaxial polysilicon wafer (polysilicon as a third layer grown on a single crystal silicon substrate through an insulation layer).
The third layer 12 is provided with a displaceable first support body 13 separated from the first layer 10 and a non-displaceable second support body 16 which is connected with the first layer 10. The first support body 13 has a mass body 15 disposed at the center and a plurality of first plates 14 extending in a direction perpendicular to the mass body 15. The second support body 16 has two mounting parts 18 straightly disposed at both ends and a plurality of second plates 17 extending in a direction perpendicular to the mounting parts 18. The second layers 11 disposed at lower parts of the plurality of first plates 14 and the mass body 15 are removed by etching so that the first support body 13 is displaceable in parallel with respect to the surface of the first layer 10.
Further, the plurality of first plates 14 and the plurality of second plates 17 respectively form comb electrodes, which, when the displaceable mass body displaces in a direction perpendicular to the first plate 14, measure an acceleration by utilizing a change in capacitance between the first plate 14 and the second plate 17. Still further, a conductor 19 for conducting these comb electrodes to an external circuit is electrically insulated from the first layer 10 by the second layer (insulation layer) 11, and further electrically insulated from the third layer 12 by a cutout 20.
In the capacitive type acceleration sensor chip using comb electrodes of this type, in order to increase the change in capacitance to affect an increase in sensitivity, it is necessary to form a structure with a decreased rigidity of a movable electrode (first plate 14). There are two factors that cause variations in sensitivity when such a sensor is constructed. A first factor is a variation in rigidity of the movable electrode (first plate 14) that is dependent on the production precision, and where the sensitivity is small when the rigidity is high. A second factor is the variation of gap between the movable electrode (first plate 14) and a fixed electrode (second plate 17), where the sensitivity decreases as the gap increases.
With respect to the first sensitivity variation factor, in general, production methods such as wet etching, RIE (Reactive Ion Etching), plasma etching and the like are used in process for producing the gap between the movable electrode and the fixed electrode and in the process of producing the support part of the movable electrode. With these production methods, since etching speed in a depth direction varies depending on the processing width, a variation occurs in the processing shape depending on the width of etching pattern. To prevent this, it is necessary to make a complex mask design in consideration of the etching speed which varies for every pattern width, resulting in a complicated process.
The second sensitivity variation factor will now be described in detail. In a sensor chip using a wafer in which polysilicon is formed as a third layer through an insulation layer on a single crystal silicon substrate or a SOI wafer, the second layer comprising an insulation layer, such as SiO.sub.2, between the first layer and the third layer and a passivation film for protecting circuits on an upper surface of the third layer are formed. As a result, there is a loss of balance in the internal stress between a surface on the side where the second and third layers are disposed on the first layer which controls the rigidity of wafer, and the opposite back surface, resulting in a warped wafer. Therefore, there is a problem in that due to such a warping of wafer, a strain occurs in the sensor structure formed on the third layer, thereby, there is variation in the gap between the movable electrode and the fixed electrode constituting the comb electrodes, for example, of the capacitive type sensor chip. Yet further, there is another problem in that in an initial state before measurement when such a detected physical amount is not yet generated, generation of a strain results in an increase in offset, which requires a complicated correction circuit.
Further, in the acceleration sensor chip, after the insulation layer is etched to form a number of sensor chips, in a subsequent process such as a dicing process to divide it into discrete chips, there is a problem in that foreign matter may enter the gaps between the comb electrodes. Also, static electricity generated during sensor operation may attract foreign matter from other packaged parts to the sensor part. Depending on the size of entering foreign matter, operation of the comb electrodes may be disturbed. Even when the size of the entering foreign matter is small enough that the matter does not disturb the operation of the comb electrodes, depending on the characteristics of the entering foreign matter, capacitance between the comb electrodes may be varied. Still further, there is another problem in that, when an epitaxial polysilicon wafer is used, since polysilicon is produced by a film forming apparatus such as a CVD apparatus, even if the same in outer dimensions, a deviation occurs in mechanical characteristics such as internal stress or breakdown stress, resulting in degraded reliability of the sensor chip.
The sensor chip is incorporated in a package 60, forming a semiconductor sensor. FIG. 3 shows an example of a prior art semiconductor sensor. In this prior art example, an acceleration sensor chip 50, for detecting an acceleration in a direction 70 perpendicular to the chip surface, is mounted on a printed circuit board 80 so that the perpendicular direction of the chip surface is correctly in line with the direction 70 of the acceleration. More specifically, a package 60 incorporating the acceleration sensor chip 50 is fixed with a sensor retaining pin 91 to a high-rigidity substrate 90, and the high-rigidity substrate 90 is mounted on the printed circuit board. Package terminals 61, electrically connected with input/output terminals (not shown) of the acceleration sensor chip, are connected to terminals 81 of the printed circuit with wiring 82. A similar construction to the semiconductor acceleration sensor shown in FIG. 3 is described in Japanese Patent Application Laid-open No. 8-94663 (1996) (U.S. patent application Ser. No. 08/189,948).
The sensor chip illustrated in FIG. 1A and FIG. 1B, for example, is used as the acceleration sensor chip 50. As for the semiconductor sensor illustrated in FIG. 3, it is possible to obtain an output according to the acceleration generated in the direction 70 perpendicular to the surface of the acceleration sensor chip 50.
However, the above-described prior art acceleration sensor has the following problems:
1) Because the acceleration sensor package 60 is mounted on the printed circuit board 80 through the high-rigidity substrate 90, the area required for mounting is increased, and the entire acceleration measuring system, including the printed circuit board 80, is increased in size. PA1 2) Mechanical vibration of the wiring 82 transmits vibration to the sensor package, resulting in mechanical noise. Further, since the wiring 82 is located in a three-dimensional space, it tends to cause an induction noise from outside the sensor chip. PA1 3) A process for fixing the package 60 to the high-rigidity substrate 90, a process for wiring from the package 60 to the printed circuit board 80 and the like are required. These processes are difficult to automate, resulting in increased assembly cost. PA1 (i) in an acceleration sensor chip using a simple piece of single crystal silicon wafer, use of a thick, large-diameter wafer is difficult, PA1 (ii) in a capacitive type acceleration sensor chip using SOI wafer or epitaxial polysilicon wafer, PA1 a) increasing the sensor sensitivity is difficult, PA1 b) in the dicing process after removing the insulation layer, foreign matter may enter the sensor structure, PA1 c) variations of sensitivity and offset are large because of the strain of sensor caused by the warping of wafer. PA1 d) detection capacity is changed by foreign matter, and PA1 e) the sensor structure possesses less reliable mechanical characteristics. PA1 a second sensor group including a second support frame part, and a plurality of second sensor structures comprising displaceable second weight parts having magnetic thin films formed on their respective surfaces and second beam parts for connecting the second weight parts to the second support frame part, the second support frame part and the second sensor structures being formed on the silicon substrate through an insulating layer, wherein the insulating layer between the plurality of sensor structures and the silicon substrate is removed, second detection coils are respectively formed surrounding the second weight parts on the second support part on the respective periphery of the second parts, and the plurality of second detection coils are connected in series, the first and second sensor groups being formed on a same semiconductor chip; PA1 the first sensor group and the second sensor group are equal in number of sensor structures, and the first sensor group and the second sensor group are disposed symmetrically about a detection axis as an axis of symmetry, PA1 the first and second detection coils of the first and second sensor groups form closed loops so that currents flowing through the plurality of first and second detection coils of the first and second sensor groups flow in the same direction when an angular acceleration generates about the detection axis. This embodiment may further comprise means for amplifying signals from the plurality of first and second detection coils and means for integrating outputs from the plurality of detection coils to output an angular acceleration signal. PA1 (a) a step for preparing a SOI wafer comprising a silicon substrate, a SiO.sub.2 layer and a silicon thin film; PA1 (b) a step for ion implanting a dopant at a position corresponding to a semiconductor strain gauge of the silicon thin film to form a diffusion resistor, and forming devices necessary for circuit construction on the silicon thin film; PA1 (c) a step for providing a protective film on the entire surface of the wafer, opening a through hole penetrating the silicon thin film by patterning and etching, and forming a weight part and a beam part connecting to a support frame part remained on the periphery; PA1 (d) while maintaining the protective film, as is, for forming the through hole, a step for removing by wet etching the SiO.sub.2 layer under the weight part and the beam part; PA1 (e) a step for removing the protective film, and coating a resist over the entire surface of the wafer; PA1 (f) a step for forming a slit by dicing for dividing the chip while maintaining a small thickness of the wafer; PA1 (g) a step for removing by ashing the resist on the wafer by an O.sub.2 plasma; and PA1 (h) a step for dividing the chip by concentrating a stress on the slit. PA1 (a) a step for preparing a SOI wafer comprising a silicon substrate, a SiO.sub.2 layer and a silicon thin film; PA1 (b) a step for ion implanting a dopant at a position corresponding to a semiconductor strain gauge of the silicon thin film to form a diffusion resistor, forming a magnetic thin film at a position corresponding to a weight part, forming a detection coil surrounding the magnetic thin film, and forming devices necessary for circuit construction on the silicon thin film; PA1 (c) a step for providing a protective film on the entire surface of the wafer, opening a through hole penetrating the silicon thin film by patterning and etching, and forming a beam part connecting to the weight part and a support frame part remained on the periphery; PA1 (d) while maintaining the protective film, as is, for forming the through hole, a step for removing by wet etching the SiO.sub.2 layer under the weight part and the beam part; PA1 (e) a step for removing the protective film, and coating a resist over the entire surface of the wafer; PA1 (f) a step for forming a slit by dicing for dividing the chip while maintaining a small thickness of the wafer; PA1 (g) a step for removing by ashing the resist on the wafer by an O.sub.2 plasma; and PA1 (h) a step for dividing the chip by concentrating a stress on the slit. PA1 a first step for forming a plurality of cutouts of a same width on the third layer to form a detection surface of the sensor structure having a beam part and a weight part for displacing the beam part which are separated from each other; PA1 a second step for filling the plurality of cutouts of the same width of the sensor structure with a sealing agent to flatten the surface of the third layer including the sensor structure; PA1 a third step for forming a circuit part connected electrically to the sensor structure in the periphery of the surface-flattened third layer; and PA1 a fourth step for removing the sealing agent filled in the plurality of cutouts of the same width and removing the second layer located beneath a detection surface of the sensor structure to make the beam part and the weight part provided on the detection surface of the sensor structure displaceable.